Conventionally, large-scale circuits are developed in which many functions are put into one large scale integration (LSI). In the development of such large-scale circuits, circuits are developed for each module by a plurality of logic designers. In a case where large-scale circuits are developed for each module, there are cases where wiring for connecting modules is difficult to be made in accordance with an increase in the scale of circuits. In order to extract such a problem in an early step and solve the extracted problem, a layout process and logic design are repeated by a developer in a state in which the specifications of circuits are undetermined.
In the layout process of such a large-scale circuit, a static timing analysis is performed in which it is determined whether or not a timing violation occurs using circuit information of each module and timing constraints applied to each module. In such a static timing analysis, an information processing apparatus is used, which determines whether or not a timing violation occurs using the circuit information and the timing constraints.
Here, an example of layout process will be described using FIG. 14. FIG. 14 is a flowchart that is used for describing the example of layout process. In the example of the layout process illustrated in FIG. 14, specifications are determined for each module in Step S1, logic design is performed in Step S2, timing constraints are generated in Step S3, and thereafter, logic synthesis of the modules is performed in Step S4. Then, after the entire circuit is built up in Step S5, in order to determine whether or not a timing violation occurs, a static timing analysis using an information processing apparatus is performed in Step S6.
In a case where a timing violation is determined not to have occurred through the static timing analysis, each module is arranged and wired in Step S7, and the static timing analysis is performed again in Step S8. Thereafter, in a case where a timing violation does not occur in the re-static timing analysis, the timing of the entire circuit is fixed in Step S9.
Here, in a case where a design error is included in the circuit of a module or in a case where there is an error in the timing constraints, a timing violation occurs in which transmission timing and reception timing between modules are out of sync. In other words, in a case where there is a design error or in a case where there is an error in the timing constraints, the information processing apparatus that performs the static timing analysis detects an occurrence of a timing violation. In such a case, a developer determines whether or not the detected timing violation is an error detection that is caused by an error in the timing constraints in a manual manner.
Here, an example of static timing analysis will be described with reference to FIG. 15. FIG. 15 is a flowchart that illustrates the example of static timing analysis. For example, in the example illustrated in FIG. 15, the developer generates timing constraints of each module in Step S10. Then, the static timing analysis using the generated timing constraints and the circuit information of each module is performed by the information processing apparatus in Step S11.
In a case where it is determined that no timing violation occurs by the information processing apparatus (No in Step S12), the timing is fixed in Step S13. On the other hand, in a case where it is determined that a timing violation has occurred by the information processing apparatus (Yes in Step S12), the developer determines whether or not the cause of the timing violation is an error detection due to an error in the timing constraints in a manual manner in Step S14.
Then, in a case where the developer determines that the cause of the timing violation is an error detection due to an error in the timing constraints (Yes in Step S14), the developer corrects the timing constraints in Step S15. On the other hand, in a case where the developer determines that the cause of the timing constraints is not an error detection due to an error in the timing constraints (No in Step S14), each module circuit is corrected in Step S16.
Here, an example will be described with reference to FIGS. 16 to 18 in which a timing violation that is caused by an error in the timing constraints is detected. FIG. 16 is a diagram that illustrates an example of setting of timing constraints. FIG. 17 is a diagram that illustrates a range to which a multi-cycle is applied. FIG. 18 is a diagram that illustrates an overlap of timing constraints.
For example, in the example illustrated in FIG. 16, a timing constraint in which the output is in multi-cycle “4” is set in module A, and a timing constraint in which the input is in multi-cycle “2” is set in module C. In such a case, as denoted by α in FIG. 17, the range from module A to module C is an application range of the multi-cycle “4”. In addition, as denoted by β in FIG. 17, the range from module A to module C and the range from module B to module C correspond to application ranges of multi-cycle “2”.
As a result, as denoted by γ in FIG. 18, the range from module A to module C is applied with two different multi-cycles “2” and “4”. In such a case, depending on a tool that is used for a static timing analysis, a different timing constraint is selected, and accordingly, a timing violation is detected.    Patent Document 1: Japanese Laid-open Patent Publication No. 2005-122578
However, in the above-described method of determining whether or not a static timing analysis is an error detection, it is determined by manpower whether or not the cause of the timing violation is an error in the timing constraints, and accordingly, there is a problem in that the number of man-hours taken for checking an error detection increases.